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PRELIMINARY DATA SHEET
128MB DDR SDRAM S.O. DIMM
EBD13UB6ALS (16M words x 64 bits, 2 Banks)
Description
The EBD13UB6ALS is 16M words x 64 bits, 2 banks Double Data Rate (DDR) SDRAM module, mounted 8 pieces of 128M bits DDR SDRAM (EDD1216ALTA) sealed in TSOP package. Read and write operations are performed at the cross points of the CLK and the /CLK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 200-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* 200-pin socket type package (dual lead out) Outline: 67.6mm (Length) x 31.75mm (Height) x 3.80mm (Thickness) Lead pitch: 0.6mm * 2.5V power supply * SSTL-2 interface for all inputs and outputs * Clock frequency: 133MHz/100MHz (max.) * Data inputs and outputs are synchronized with DQS * 4 banks can operate simultaneously and independently (Component) * Burst read/write operation * Programmable burst length: 2, 4, 8 Burst read stop capability * Programmable burst sequence Sequential Interleave * Start addressing capability Even and Odd * Programmable /CAS latency (CL): 2, 2.5 * 4096 refresh cycles: 15.6s (4096/64ms) * 2 variations of refresh Auto refresh Self refresh
Document No. E0219E10 (Ver. 1.0) Date Published October 2001 (K) Printed in Japan URL: http://www.elpida.com
C
Elpida Memory, Inc. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
EBD13UB6ALS
Ordering Information
Part number EBD13UB6ALS-7A EBD13UB6ALS-75 EBD13UB6ALS-1A Clock frequency MHz (max.) 133 133 100 /CAS latency 2.0 2.5 2.0 Package 200-pin S.O. DIMM Contact pad Gold Mounted devices EDD1216ALTA
Pin Configurations
Front side 1 pin 39 pin 41 pin 199 pin
2 pin
40 pin 42 pin Back side
200 pin
Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
Pin name VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CLK0 /CLK0 VSS DQ16 DQ17 VDD DQS2 DQ18
Pin No. 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
Pin name VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD NC NC VSS NC NC VDD NC NC VSS CLK2 /CLK2 VDD NC NC NC
Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
Pin name VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22
Pin No. 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
Pin name VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD NC NC VSS NC NC VDD NC NC VSS VSS VDD VDD CKE0 NC A11
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
Pin No. 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149
Pin name A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /CS0 NC VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS
Pin No. 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
Pin name DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID
Pin No. 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
Pin name A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /CS1 NC VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS
Pin No. 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
Pin name DQ46 DQ47 VDD /CLK1 CLK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 NC
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
Pin Description
Pin name A0 to A11 BA0, BA1 DQ0 to DQ63 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CLK0 to CLK2 /CLK0 to /CLK2 DQS0 to DQS7 DM0 to DM7 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS VDDID NC Function Address input Row address Column address A0 to A11 A0 to A8
Bank select address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground VDD indentication flag No connection
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
Serial PD Matrix
Byte No. 0 1 2 3 4 5 6 7 8 9 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM banks Module data width Module data width continuation Bit7 1 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Bit5 Bit4 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Bit3 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit2 Bit1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit0 Hex value 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 80H 08H 07H 0CH 09H 02H 40H 00H 04H 75H 75H A0H 75H 75H 80H 00H 80H 10H 00H 01H 0EH 04H 0CH 01H 02H 20H 00H 75H A0H A0H 80H 75H 80H 00H Comments 128 bytes 256 bytes DDR SDRAM 12 9 2 64 0 SSTL2 7.5ns 7.5ns 10ns 0.75ns 0.75ns 0.8ns None. Norm x 16 None. 1 CLK 2,4,8 4 2, 2.5 0 1 Differential Clock VDD 0.2V 7.5ns 10ns 10ns 0.80ns 0.75ns 0.8ns
Voltage interface level of this assembly 0 DDR SDRAM cycle time, CL = 2.5 -7A -75 -1A 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1
10
SDRAM access from clock (tAC) -7A -75 -1A
11 12 13 14 15 16 17 18 19 20 21 22 23
DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time at CL = 2 -7A -75 -1A
24
Maximum data access time (tAC) from 1 clock at CL = 2 -7A -75 -1A 0 1 0
25 to 26
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
Byte No. 27 Function described Minimum row precharge time (tRP) -7A -75 -1A 28 Minimum row active to row active delay (tRRD) -7A -75 -1A 29 Minimum /RAS to /CAS delay (tRCD) -7A -75 -1A 30 Minimum active to precharge time (tRAS) -7A -75 -1A 31 32 Module bank density Address and command setup time before clock (tIS) -7A -75 -1A 33 Bit7 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Bit6 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 1 0 Bit5 Bit4 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 0 Bit3 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Bit2 Bit1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Bit0 Hex value 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50H 50H 50H 3CH 3CH 3CH 50H 50H 50H 2DH 2DH 32H 10H 90H 90H B0H 90H 90H B0H 50H 50H 60H 50H 50H 60H 00H 00H 74H 94H 3AH FEH 00H Elpida Memory Comments 20ns 20ns 20ns 15ns 15ns 15ns 20ns 20ns 20ns 45ns 45ns 50ns 64M bytes 0.9ns 0.9ns 1.1ns 0.9ns 0.9ns 1.1ns 0.5ns 0.5ns 0.6ns 0.5ns 0.5ns 0.6ns
Address and command hold time after 1 clock (tIH) -7A -75 -1A 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0
34
Data input setup time before clock (tDS) -7A -75 -1A
35
Data input hold time after clock (tDH) -7A -75 -1A
36 to 61 62 63
Superset information SPD Revision Checksum for bytes 0 to 62 -7A -75 -1A
64 65 to 71 72 73 to 90 91 to 92 93 to 94
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Manufacturer's part number Revision code Manufacturing date
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
Byte No. 95 to 98 99 to 127 Function described Module serial number Manufacture specific data Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Block Diagram
/CS1 /CS0 RS DQS0 RS DM0 8 DQ0 to DQ7 RS DQS1 RS DM1 8 DQ8 to DQ15 RS I/O8 to I/O15 I/O8 to I/O15 DQ40 to DQ47 RS I/O0 to I/O7 UDQS UDM I/O0 to I/O7 UDQS UDM DQ32 to DQ39 RS DQS5 RS DM5 8 RS I/O8 to I/O15 RS DQS6 RS LDM 8 DQ16 to DQ23 RS DQS3 RS DM3 8 DQ24 to DQ31 RS I/O8 to I/O15 I/O8 to I/O15 DQ56 to DQ63 RS I/O0 to I/O7 UDQS UDM I/O0 to I/O7 UDQS UDM DQ48 to DQ55 RS DQS7 RS DM7 8 RS I/O8 to I/O15 I/O8 to I/O15 UDM UDM UDQS LDM DM6 8 RS I/O0 to I/O7 I/O0 to I/O7 UDQS LDM LDM LDQS I/O8 to I/O15 UDM UDM UDQS LDM LDM DM4 8 RS I/O0 to I/O7 I/O0 to I/O7 UDQS LDQS RS DQS4 RS LDM LDM LDQS
/CS
LDQS
/CS
/CS
LDQS
/CS
D0
D4
D2
D6
RS DQS2 RS DM2 LDQS
/CS
LDQS
/CS
/CS
LDQS
/CS
D1
D5
D3
D7
* D0 to D7 : EDD1216ALTA U0 : 2k bits EEPROM Rs : 22
BA0 to BA1 A0 to A11 /RAS /CAS /WE CKE0 CKE1 VDDSPD VREF VDD
Serial PD SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D3) SDRAMs (D4 to D7) SPD SDRAMs (D0 to D7) SDRAMs (D0 to D7), VDD and VDDQ CLK0 /CLK0 CLK1 /CLK1 CLK2 10 pF /CLK2 Notes : Open 1. DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. VDDID strap connections: (for memory device VDD, VDDQ) Strap out (open): VDD = VDDQ Strap in (closed): VDD VDDQ 2. The SDA pull-up registor is reguired due to the open-drain/open-collector output. 3. The SCL pull-up registor is recommended, because of the normal SCL lime inactive "high" state. SDRAMs (D0, D1, D4, D5) SDRAMs (D2, D3, D6, D7) SCL SA0 SA1 SA2 SCL A0 A1 A2 SDA SDA
U0
VSS VDDID
SDRAMs (D0 to D7), SPD
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
Logical Clock Net Structure
4DRAM loads DRAM1
120 DIMM connector
DRAM2
DRAM3
DRAM4
Pin Functions (1)
CLK, /CLK (input pin): The CLK and the /CLK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CLK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CLK and the /CLK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CLK and the /CLK. /CS (input pin): When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A11 (input pins): Row address (AX0 to AX11) is determined by the A0 to the A11 level at the cross point of the CLK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY8) is loaded via the A0 to the A8 at the cross point of the CLK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected. CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. The CKE level must be kept for 1 CLK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the CLK rising edge and the VREF level with proper setup time tIS, at the next CLK rising edge CKE level must be kept with proper hold time tIH.
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
Pin Functions (2)
DQ (input and output pins): Data are input to and output from these pins. DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input). DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and VREF VDD (power supply pins): 2.5V is applied. VDDSPD (power supply pin): 2.5V is applied (For serial EEPROM). VSS (power supply pin): Ground is connected.
Detailed Operation Part, AC Characteristics and Timing Waveforms
Refer to the EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Series datasheet (E0136E).
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 1ms and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VDD IO PD TA Tstg Value -0.5 to +3.6 -0.5 to +3.6 50 8 0 to +70 -55 to +125 Unit V V mA W C C Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +70C)
Parameter Supply voltage Symbol VDD VSS Input reference voltage Termination voltage DC Input high voltage DC Input low voltage DC Input signal voltage DC differential input voltage VREF VTT VIH VIL VIN (dc) min. 2.3 0 0.49 x VDD VREF - 0.04 VREF + 0.18 -0.3 -0.3 Typ 2.5 0 -- VREF -- -- -- -- max. 2.7 0 0.51 x VDD VREF + 0.04 VDD + 0.3 VREF - 0.18 VDD+ 0.3 VDD + 0.6 Unit V V V V V V V V 1 1 1, 2 1, 3 4 5 Notes 1
VSWING (dc) 0.36
Notes: 1. 2. 3. 4. 5.
All parameters are referred to VSS, when measured. VIH is allowed to exceed VDD up to 4.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to -1.0V for the period shorter than or equal to 5ns. VIN (dc) specifies the allowable dc execution of each differential input. VSWING (dc) specifies the input differential voltage required for switching.
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
DC Characteristics 1 (TA = 0 to +70C, VDD = 2.5V 0.2V, VSS = 0V)
Parameter Operating current (ACTV-PRE) Symbol ICC0 Grade -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A max. TBD Unit mA Test condition CKE VIH, tRC = tRC (min.) CKE VIH, BL = 2, CL = 3.5, tRC = tRC (min.) CKE VIL Notes 1, 2, 5
Operating current (ACTV-READICC1 PRE) Idle power down standby current ICC2P
TBD
mA
1, 2, 5
TBD
mA
4
Idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current
ICC2N
TBD
mA
CKE VIH, /CS VIH
4
ICC3P
TBD
mA
CKE VIL CKE VIH, /CS VIH tRAS = tRAS (max.) CKE VIH, BL = 2, CL = 3.5 CKE VIH, BL = 2, CL = 3.5 tRFC = tRFC (min.) Input VIL or VIH Input VDD - 0.2V Input 0.2V.
3
ICC3N
TBD
mA
3
ICC4R
TBD
mA
1, 2, 5, 6
ICC4W
TBD
mA
1, 2, 5, 6
ICC5
TBD
mA
Self refresh current
ICC6
TBD
mA
Notes. 1. 2. 3. 4. 5. 6. 7.
These ICC data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. The ICC data on this table are measured with regard to tCK = tCK (min.) in general.
DC Characteristics 2 (TA = 0 to +70C, VDD = 2.5V 0.2V, VSS = 0V)
Parameter Input leakage current Output leakage current Output high current Output low current Symbol ILI ILO IOH IOL min. -16 -10 -15.2 15.2 max. 16 10 -- -- Unit A A mA mA Test condition VDD VIN VSS VDD VOUT VSS VOUT = 1.95V VOUT = 0.35V Notes
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
Pin Capacitance (TA = 25C, VDD = 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data and DQS input/output capacitance Symbol CI1 CI2 CO Pins max. Unit pF pF pF Notes
Address, /RAS, /CAS, /WE, TBD /CS, CKE CLK, /CLK DQ, DQS TBD TBD
AC Characteristics (TA = 0 to +70C, VDD = 2.5V 0.2V, VSS = 0V) Synchronous Characteristics
-7A Parameter Clock cycle time CL = 2.5 CL = 2 CLK high-level width CLK low-level width DQ output access time from CLK, /CLK DQS output access time from CLK, /CLK tCH tCL tAC Symbol tCK min. 7.5 7.5 0.45 0.45 -0.75 max. 12 12 0.55 0.55 0.75 0.75 0.5 0.5 0.75 0.75 -- 1.1 0.6 -75 min. 7.5 10 0.45 0.45 -0.75 -0.75 -- -- -0.75 -0.75 tCH, tCL 0.9 0.4 max. 12 12 0.55 0.55 0.75 0.75 0.5 0.5 0.75 0.75 -- 1.1 0.6 -1A min. 10 10 0.45 0.45 -0.8 -0.8 -- -- -0.8 -0.8 max. 12 12 0.55 0.55 0.8 0.8 0.6 0.6 0.8 0.8 Unit ns ns tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns ns ns tCK Note
tDQSCK -0.75 --
DQS-DQ skew (for DQS and associated DQ tDQSQ signals)
DQS-DQ skew (for DQS and all DQ signals) tDQSQA -- Data out low-impedance time from CLK, /CLKtLZ Data out high-impedance time from CLK, /CLK Half clock period Read preamble Read postamble DQ/DQS output hold time from DQS DQ and DM input setup time DQ and DM input hold time tHZ tHP tRPRE tRPST tQH tDS tDH -0.75 -0.75 tCH, tCL 0.9 0.4
tCH, tCL -- 0.9 0.4 1.1 0.6
tHP - 0.75 -- 0.5 0.5 1.75 -- -- -- -- -- 0.6 1.25 -- -- -- -- -- -- -- --
tHP - 0.75 -- 0.5 0.5 1.75 0 0.25 0.4 0.75 0.35 0.35 0.2 0.2 0.9 0.9 2.2 1 -- -- -- -- -- 0.6 1.25 -- -- -- -- -- -- -- --
tHP - 1 -- 0.6 0.6 2 0 0.25 0.4 0.75 0.35 0.35 0.2 0.2 1.1 1.1 2.5 1 -- -- -- -- -- 0.6 1.25 -- -- -- -- -- -- -- --
DQ and DM input pulse width (for each input) tDIPW Write preamble setup time Write preamble Write postamble Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CLK setup time DQS falling edge hold time from CLK Address and control input setup time Address and control input hold time Address and control input pulse width Internal write to read command delay
tWPRES 0 tWPRE tWPST tDQSS tDQSH tDQSL tDSS tDSH tIS tIH tIPW tWTR 0.25 0.4 0.75 0.35 0.35 0.2 0.2 0.9 0.9 2.2 1
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
Synchronous Characteristics Example
tCK Symbol tCH tCL tRPRE tRPST tWPRE tWPST tDQSS tDQSH tDQSL tDSS tDSH tWTR 7.5 ns min. 3.4 3.4 6.75 3 0.25 3 5.6 2.63 2.63 1.5 1.5 7.5 max. 4.1 4.1 8.25 4.5 -- 4.5 9.4 -- -- -- -- -- 10 ns min. 4.5 4.5 9 4 2.5 4 7.5 3.5 3.5 2 2 10 max. 5.5 5.5 11 6 -- 6 12.5 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
Asynchronous Characteristics
-7A Parameter ACT to REF/ACT command period (operation) REF to REF/ACT command period (refresh) ACT to PRE command period PRE to ACT command period ACT to READ/WRITE delay ACT(one) to ACT(another) command period Write recovery time Auto precharge write recovery time + precharge time Mode register set command cycle time Exit self refresh to command Average periodic Refresh interval Symbol tRC tRFC tRAS tRP tRCD tRRD tWR tDAL tMRD tXSNR tREF1 min. 65 75 45 20 20 15 2 TBD 15 75 -- max. -- -- 120,000 -- -- -- -- -- -- -- 15.6 -75 min. 65 75 45 20 20 15 2 TBD 15 75 -- max. -- -- 120,000 -- -- -- -- -- -- -- 15.6 -1A min. 70 80 50 20 20 15 2 TBD 15 80 -- max. -- -- 120,000 -- -- -- -- -- -- -- 15.6 Unit ns ns ns ns ns ns CLK ns ns ns s
Preliminary Data Sheet E0219E10 (Ver. 1.0)
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EBD13UB6ALS
Physical Outline
Unit: mm 63.60 11.55 18.45 3.80 max. (DATUM -A-)
4x Full R
Component area (Front)
20.0 4.00
31.75 6.00
2.15
11.40 0.05 4.20 0.05
A
47.40 0.05
B 2.45 1.00 0.10
67.60 0.15
4.20 0.05 1.50 2.45
2
199
1
11.40 0.05
47.40 0.05
200
2.15 R0.50 0.20
R0.50 0.20
2x 1.80
Component area (Back)
4.00 0.10
(DATUM -A-)
2.00 min.
Detail A
(DATUM -A-) FULL R
4.00 0.10
Detail B
2.55 min.
0.60 1.80 1.00 0.10 0.45 0.05
Preliminary Data Sheet E0219E10 (Ver. 1.0)
14
0.25 max.
EBD13UB6ALS
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0107
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E0219E10 (Ver. 1.0)
15
EBD13UB6ALS
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Preliminary Data Sheet E0219E10 (Ver. 1.0)
16

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